THREAD PAUSE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

摘要

According to one aspect of the present invention, a processor includes a decode unit decoding a thread pause instruction from a first thread. A back end part of the processor is connected to the decode unit. The back end part of the processor pauses processes of follow-up instructions of a first thread for execution in response to the thread pause instruction. The follow-up instructions occur after the thread pause instruction in a program sequence. In addition, the processor maintains at least most of the back end part of the processor in a state where the instructions of the first thread except for the thread pause instruction are lacking for a predetermined period of time in response to the thread pause instruction. Most of the back end part of the processor can include a plurality of execution units and an instruction cue unit.