METHOD FOR MANUFACTURING TFT BACKPLANE AND STRUCTURE OF TFT BACKPLANE

摘要

The present invention provides method for manufacturing a TFT backplane and a structure of a TFT backplane. The method includes (1) forming a gate terminal (2) and a first metal electrode M1 on a substrate (1); (2) sequentially forming a gate insulation layer (3), a semiconductor layer, and an etch stop layer on the gate terminal (2), the first metal electrode M1, and the substrate (1) in a successive manner and applying a photolithographic operation to form an island-like semiconductor layer (4) and an island-like etch stop layer (5); (3) applying a photolithographic operation to patternize the island-like etch stop layer (5) and the gate insulation layer (3) to form a plurality of etch stop layer vias (51) and a gate insulation layer via (31); (4) forming source/drain terminals (6) and a second metal electrode M2; (5) forming a passivation protection layer (7); (6) forming a planarization layer (8); (7) forming a pixel electrode layer (9); (8) forming a pixel definition layer (10); and (9) forming a spacer pillar (11).

主权项

1. A method for manufacturing a thin-film transistor (TFT) backplane, comprising the following steps:
(1) providing a substrate, forming a first metal layer on the substrate and patternizing the first metal layer so as to form a gate terminal on one side portion of the substrate and a first metal electrode M1 on an opposite side portion of the substrate; (2) successively forming a gate insulation layer, a semiconductor layer, and an etch stop layer on the gate terminal, the first metal electrode M1, and the substrate and applying a photolithographic operation to patternize the semiconductor layer and the etch stop layer so as to form an island-like semiconductor layer and an island-like etch stop layer; (3) applying a photolithographic operation to patternize the island-like etch stop layer and the gate insulation layer so as to form a plurality of etch stop layer vias and a gate insulation layer via to respectively expose portions of the semiconductor layer and a portion of the gate terminal; (4) forming a second metal layer on the island-like etch stop layer and the gate insulation layer and patternizing the second metal layer to form source/drain terminals on one side portion of the substrate and a second metal electrode M2 on an opposite side portion of the substrate, wherein the source/drain terminals fill up the plurality of etch stop layer vias to connect to the semiconductor layer and the source/drain terminals fill up the gate insulation layer via to connect to the gate terminal; and a portion of the gate insulation layer that is located on said opposite side portion of the substrate is sandwiched between the second metal electrode M2 and the first metal electrode M1; (5) forming a passivation protection layer on the source/drain terminals and the second metal electrode M2 and patternizing the passivation protection layer; (6) forming a planarization layer on the passivation protection layer and patternizing the planarization layer; (7) forming a pixel electrode layer on the planarization layer and patternizing the pixel electrode layer, wherein the pixel electrode is connected to the source/drain terminals; and (8) forming a pixel definition layer on the pixel electrode layer and the planarization layer and patternizing the pixel definition layer.