发明名称 Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same
摘要 A tunneling field-effect transistor (TFET) device is disclosed. A protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the protrusion structure and extends to a bottom portion of the protrusion structure as a raised drain region. A drain contact is disposed over the drain region and overlap with the isolation feature.
申请公布号 US2016027898(A1) 申请公布日期 2016.01.28
申请号 US201514874398 申请日期 2015.10.03
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Chuang Harry-Hak-Lay;Kuo Cheng-Cheng;Zhu Ming
分类号 H01L29/66;H01L29/06 主分类号 H01L29/66
代理机构 代理人
主权项 1. A method for forming a field effect transistor (FET), the method comprising: providing a substrate; etching the substrate to form a protrusion on a surface of the substrate; forming isolation features on the substrate; doping a portion of the substrate adjacent to the protrusion to form a drain region between the isolation features, including doping a lower portion of the protrusion to form a raised drain region; forming a first isolation dielectric layer over the drain region; forming a gate stack having a planar portion over the drain region, which is parallel to the surface of the substrate and has a sidewall and a gating surface, which wraps around a middle portion of the protrusion and which overlaps with the raised drain region; forming a second isolation dielectric layer over the planar portion of the gate stack and the raised drain region; recessing a portion of the gating surface of the gate stack to expose a top portion of the protrusion; forming a source region on the top portion of the protrusion with a different doping type than the drain region, the source region overlapping with the gating surface of the gate stack; forming a third isolation dielectric layer over the source region, the gate stack and the second isolation dielectric layer; forming a drain contact on the drain region and a portion of one of the isolation features together; and simultaneously with the drain contact formation, forming a gate contact on the planar portion of the gate stack and the sidewall of the planar portion of the gate stack, the gate contact extending through a portion of the isolation dielectric layer, and forming a source contact on the source region.
地址 Hsin-Chu TW