MULTI-LANE N-FACTORIAL (N!) AND OTHER MULTI-WIRE COMMUNICATION SYSTEMS

摘要

System, methods and apparatus are described that facilitate communication of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A receiving device receives a sequence of symbols over a multi-wire link. The receiving device further receives a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link. The receiving device decodes the sequence of symbols using the clock signal. In an aspect, a second clock signal is embedded in guaranteed transitions between pairs of consecutive symbols in the sequence of symbols. Accordingly, the receiving device decodes the sequence of symbols using the clock signal received via the dedicated clock line while ignoring the second clock signal.

主权项

1. A receiving device, comprising:
a processing circuit configured to:
receive a sequence of symbols over a multi-wire link,receive a clock signal via a dedicated clock line, wherein the dedicated clock line is separate from, and in parallel with, the multi-wire link, anddecode the sequence of symbols using the clock signal.