发明名称 |
SYSTEMS AND METHODS FOR WAFER-LEVEL LOOPBACK TEST |
摘要 |
Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path. |
申请公布号 |
US2016025807(A1) |
申请公布日期 |
2016.01.28 |
申请号 |
US201414339224 |
申请日期 |
2014.07.23 |
申请人 |
QUALCOMM Incorporated |
发明人 |
Loke Alvin Leng Sun;Bryan Thomas Clark;Jalilizeinali Reza;Wee Tin Tin;Knol Stephen Robert;Peterson LuVerne Ray |
分类号 |
G01R31/3177 |
主分类号 |
G01R31/3177 |
代理机构 |
|
代理人 |
|
主权项 |
1. A circuit comprising:
a die having a plurality of bits, each bit having:
a transmit data path and a receive data path;a transmit clock tree feeding the respective transmit data path of each bit; anda receive clock tree feeding the respective receive data path of each bit; wherein the transmit clock tree feeds the receive clock tree through a conductive clock node exposed on a surface of the die. |
地址 |
San Diego CA US |