发明名称 CRYPTOGRAPHIC SUPPORT INSTRUCTIONS
摘要 A data processing system includes a single instruction multiple data register file and single instruction multiple processing circuitry. The single instruction multiple data processing circuitry supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.
申请公布号 US2016026806(A1) 申请公布日期 2016.01.28
申请号 US201514792796 申请日期 2015.07.07
申请人 ARM Limited 发明人 HORSNELL Matthew James;GRISENTHWAITE Richard Roy;BILES Stuart David;KERSHAW Daniel
分类号 G06F21/60;G06F9/38;G06F9/30 主分类号 G06F21/60
代理机构 代理人
主权项 1. Data processing apparatus comprising: a single instruction multiple data register file; and single instruction multiple data processing circuitry coupled to said single instruction multiple data register file and configured to be controlled by a single instruction multiple data program instruction to perform a processing operation independently upon separate data elements stored within separate lanes within an input operand register of said single instruction multiple data register file; wherein said single instruction multiple data processing circuitry is configured to be controlled by a first further program instruction and a second further program instruction to perform a further processing operation upon an input digest data value to generate an output digest data value, the first further program instruction being operable to generate a first output operand representative of a first portion of the output digest data value, the second further program instruction being operable to generate a second output operand representative of a remaining portion of the output digest data value, and wherein the input digest data value comprises a sequence of data elements held within said single instruction multiple data register file, said first portion and said second portion of the output digest data value being dependent upon all data elements within said sequence of data elements.
地址 Cambridge GB