| 摘要 |
PROBLEM TO BE SOLVED: To expand a write margin and a read-out margin by a simpler circuit configuration in an SRAM.SOLUTION: A memory circuit 100 includes a memory cell 1, access transistors SW1, SW2, and a memory output resistance adjusting unit 3. In the memory cell 1, two CMOS inverters INV1, INV2 are complementarily connected. The access transistor SW1, SW2 has a first terminal connected to data output node Out1, Out2, a second terminal connected to bit line BL, /BL, and a third terminal to which a word voltage VDDW is input. The memory output resistance adjusting unit 3 forms a memory output resistance having a resistance value Requal to or more than a first multiple of a resistance value Rof a connection resistance. In a read-out operation, the resistance value Rof the connection resistance is a second multiple of a resistance value Rbetween a source and a drain of an nMOS transistor or a pMOS transistor in an ON state of the CMOS inverters INV1, INV2. |
