Video encoding and video/audio/data multiplexing device

摘要

The present invention provides a buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of the encoding task and quicker through-put time. The invention teaches a single chip digital signal processing device for real time video/audio compression comprising a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.

主权项

1. A multiplexing processor comprising:
a first video storage unit operable to accumulate compressed video data received from a bitstream processor at a first real time rate, and transfer the accumulated compressed video data to an external memory unit at a first burst rate, by adjusting the first real time rate to an external communication rate of the external memory unit; a second video storage unit operable to receive compressed video data from the external memory unit at a second burst rate, and transfer the received compressed video data to a video processor at a second real time rate, by adjusting the second burst rate to an internal communication rate of the multiplexing processor; the external memory unit comprising
a first buffer operable to receive the compressed video data from said first storage unit at the first burst rate, anda second buffer operable to retrieve the compressed video data from said first buffer, and transfer the retrieved data to the second video storage unit at the second burst rate, thereby allowing a difference between the first burst rate and the second burst rate; and a video processor operable to retrieve the compressed video data from said second buffer via the second video storage unit at the second real time rate.