Excess-fours processing in direct digital synthesizer implementations

摘要

Systems and methods for a split phase accumulator having a plurality of sub phase accumulators are provided, Each sub phase accumulator receives a portion of a frequency control word. The first sub phase accumulator includes a first register and the remaining sub phase accumulators include a register and an overflow register. At each discrete point in time, the first sub phase accumulator is configured to be responsive to the first portion of the frequency control word at that discrete point in time and to the first sub phase accumulator value at the immediately previous discrete point in time, and each of the remaining sub phase accumulators is configured to be responsive to a value of its corresponding portion of the frequency control word at that discrete point in time and to the same second sub phase accumulator value at the immediately previous discrete point in time.

主权项

1. A system comprising:
a phase accumulator configured to receive a frequency control word as an input, the phase accumulator comprising:
a first accumulator including a first register, the first accumulator configured to receive a first portion of the frequency control word, anda second accumulator configured to receive a second portion of the frequency control word, wherein the second accumulator includes a second register and an overflow register,wherein the phase accumulator is configured to produce a sequence of normalized rotation angles, each normalized rotation angle being based on a current value of the first accumulator and a current value of the second accumulator, andwherein the first accumulator and the second accumulator operate simultaneously in a first output data cycle, and a fine rotation stage, coupled to the phase accumulator, wherein the overflow register delays a carry-in to the first accumulator until a second output data cycle and wherein the fine rotation stage is responsive to the carry-in during the first output data cycle.