Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length

摘要

A metal-oxide-semiconductor transistor (MOS) and method of fabricating the same, in which the effective channel length is increased relative to the width of the gate electrode. A dummy gate electrode overlying dummy gate dielectric material is formed at the surface of the structure, with self-aligned source/drain regions, and dielectric spacers on the sidewalls of the dummy gate structure. The dummy gate dielectric underlies the sidewall spacers. Following removal of the dummy gate electrode and the underlying dummy gate dielectric material, including from under the spacers, a silicon etch is performed to form a recess in the underlying substrate. This etch is self-limiting on the undercut sides, due to the crystal orientation, relative to the etch of the bottom of the recess. The gate dielectric and gate electrode material are then deposited into the remaining void, for example to form a high-k metal gate MOS transistor.

主权项

1. A method of fabricating a metal-oxide-semiconductor field-effect transistor formed at a surface of single-crystal silicon, the surface having a first conductivity type, the method comprising:
forming dummy gate dielectric at a selected location of the surface, the selected location of the surface having a first conductivity type; forming a dummy gate electrode overlying the dummy gate dielectric at the selected location; forming dielectric structures on opposing sides of the dummy gate electrode, portions of the dielectric structures overlying portions of the dummy gate dielectric; forming source/drain regions of a second conductivity type into the surface at locations on opposite sides of the dummy gate electrode; then removing the first dummy gate electrode; etching the dummy gate dielectric material from the selected location of the surface and under portions of the dielectric structures; etching a recess into the silicon at locations between and under the dielectric structures; forming a gate dielectric layer at the surface of the recess; and forming a gate electrode overlying the gate dielectric layer and between the dielectric structures, the gate electrode having portions extending under the dielectric structures.