Limited range vector memory access instructions, processors, methods, and systems

摘要

A processor of an aspect includes a plurality of packed data registers. The processor also includes a unit coupled with the packed data registers. The unit is operable, in response to a limited range vector memory access instruction. The instruction is to indicate a source packed memory indices, which is to have a plurality of packed memory indices, which are to be selected from 8-bit memory indices and 16-bit memory indices. The unit is operable to access memory locations, in only a limited range of a memory, in response to the limited range vector memory access instruction. Other processors are disclosed, as are methods, systems, and instructions.

主权项

1. A processor comprising:
a plurality of packed data registers; and a unit coupled with the packed data registers, the unit operable, in response to a limited range vector memory access instruction that is to indicate a source packed memory indices that is to have a plurality of packed memory indices selected from 8-bit memory indices and 16-bit memory indices, to access memory locations, in only a limited range of a memory, in response to the limited range vector memory access instruction.