Oro and orpro with bit line trench to suppress transport program disturb

摘要

Memory devices having improved TPD characteristics and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line openings containing a bit line dielectric between the memory cells. The memory cell contains a charge storage layer and a first poly gate. The bit line opening extends into the semiconductor substrate. By containing the bit line dielectric in the bit line openings that extend into the semiconductor substrate, the memory device can improve the electrical isolation between memory cells, thereby preventing and/or mitigating TPD.

主权项

1. A memory device structure comprising: two memory cell structures on a semiconductor substrate, each of the structures comprising two undercut openings separated by a dielectric, said openings being disposed under a monolithic first poly gate wherein said monolithic first poly gate defines the upper surface of each of said undercut openings, a charge storage node positioned within each undercut opening, wherein the charge storage node comprises one of an oxide/nitride/oxide tri-layer, an oxide/nitride bi-layer, a nitride/oxide bi-layer, an oxide/tantalum oxide bi-layer (Si02/Ta205), an oxide/tantalum oxide/oxide tri-layer (Si02FFa205/Si02), an oxide/strontium titanate bi-layer (Si02/SrTi03), an oxide/barium strontium titanate bi-layer (Si02/BaSrTi02), an oxide/strontium titanate/oxide tri-layer (Si02/SrTi03/Si02), an oxide/strontium titanate/barium strontium titanate tri-layer (Si02/SrTi03/BaSrTi02) and an oxide-nitride-polysilicon-nitride-oxide (ORPRO);
a bit line opening, comprising a bit line trench, disposed between the two structures wherein the trench extends into the semiconductor substrate; spacers along the bit line openings, the spacers extending into the semiconductor substrate; the bit line openings comprising p-type pocket implant regions disposed therein, the pocket implant regions adjacent and below said charge storage nodes wherein an upper boundary of each pocket implant region is congruent with a lower boundary of the adjacent charge storage node and a first n-type bit line implant region, having a first width, disposed within the bit line opening adjacent to and extending below said pocket implant regions.