Clock phase compensator for multi-stage time division multiplexer

摘要

An upstream multiplexer multiplexes data into first and second serialized data streams based on first and second low frequency clocks each derived from a high frequency clock. A downstream multiplexer multiplexes the first and second serialized data streams into a third serialized data stream based on the high frequency clock. A timing error detector derives an error signal indicative of a phase-misalignment between the high frequency clock and the first and second serialized data bit streams based on the high frequency clock and the first and second low frequency clocks. A phase adjuster adjusts phases of the first and second low frequency clocks relative to the high frequency clock based on the error signal so as to reduce the phase-misalignment.

主权项

1. An apparatus comprising:
a first multiplexer configured to multiplex data bits into first and second serialized data bit streams based on phase-offset first and second low frequency clocks each derived from a high frequency clock; a second multiplexer configured to multiplex the first and second serialized data bit streams into a third serialized data bit stream based on the high frequency clock; a timing error detector configured to derive an error signal indicative of a phase-misalignment between the high frequency clock and the first and second serialized data bit streams based on the high frequency clock and the first and second low frequency clocks; and a phase adjuster configured to adjust phases of the first and second low frequency clocks relative to the high frequency clock based on the error signal so as to reduce the phase-misalignment.