发明名称 AN EFFECTIVE CAPACITANCE MULTIPLYING PLL WITH TWO VOLTAGE CONTROLLED OSCILLATOR GAINS
摘要 According to the present invention, a phase locked loop device comprises receives a first signal from a loop filter through a first input terminal to convert the first signal to have the value of a first slope and receives a second signal from the loop filter through a second input terminal to convert the second signal to have the value of a second slope so as to control a slope ratio of the values of the first and second slopes, thereby reducing capacitance of the loop filter by using two gain values to be easily integrated in one chip.
申请公布号 KR20160008821(A) 申请公布日期 2016.01.25
申请号 KR20140089033 申请日期 2014.07.15
申请人 PUKYONG NATIONAL UNIVERSITY INDUSTRY-UNIVERSITY COOPERATION FOUNDATION 发明人 CHOI, YOUNG SHIG
分类号 H03L7/093;H03L7/099 主分类号 H03L7/093
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