LEAKAGE CURRENT DETECTION DEVICE AND NONVOLATILE MEMORY DEVICE HAVING THE SAME

摘要

A leakage current detection device includes a test detection circuit, a reference detection circuit, a comparator, and a latch circuit. The test detection circuit is coupled between a test node and a test line, provides a voltage to the test node to charge the test line, floats the test node and the test line, and decreases a voltage of the test node based on leakage current of the test line. The reference detection circuit is coupled between a reference node and a reference line, provides the voltage to the reference node to charge the reference line, floats the reference node and the reference line, and decreases a voltage of the reference node based on self-discharge of the reference line. The comparator outputs a comparison signal by comparing voltages of the test node and the reference node. The latch circuit latches the comparison signal to output a test result signal.

主权项

1. A leakage current detection device for a nonvolatile memory device having a memory cell array coupled to drive lines, the leakage current detection device comprising:
a test detection circuit coupled between a test node and a test line, which corresponds to a first drive line coupled to the memory cell array of the nonvolatile memory device, the test detection circuit being configured to provide a supply voltage to the test node to charge the test line, to float the test node and the test line, and to decrease a voltage of the test node based on a leakage current flowing from the test line; a reference detection circuit coupled between a reference node and a reference line, which corresponds to a second drive line that is coupled to the memory cell array of the nonvolatile memory device and is configured to deliver a same type of a drive signal as the first drive line, the reference detection circuit being configured to provide the supply voltage to the reference node to charge the reference line, to float the reference node and the reference line, and to decrease a voltage of the reference node based on a self-discharge of the reference line; a comparator configured to output a comparison signal by comparing the voltage of the test node with the voltage of the reference node; and a latch circuit configured to latch the comparison signal in response to a latch control signal, and to output the latched comparison signal as a test result signal.