| 发明名称 |
SEMICONDUCTOR MEMORY DEVICE |
| 摘要 |
A semiconductor memory device includes a memory cell, a peripheral circuit configured to drive the memory cell, and a protection element. The peripheral circuit includes a first p-type MOS transistor including a gate electrode and a gate insulating film having a first film thickness, a second p-type MOS transistor including a gate electrode and a gate insulating film having a second film thickness, and an n-type MOS transistor. The gate electrode of the first p-type MOS transistor is connected to the protection element. The gate electrodes included in the second p-type MOS transistor and the n-type MOS transistor are connected only to an impurity region of another transistor or only to a gate electrode of the another transistor. |
| 申请公布号 |
US2016019965(A1) |
申请公布日期 |
2016.01.21 |
| 申请号 |
US201514629105 |
申请日期 |
2015.02.23 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
WATANABE SHOICHI |
| 分类号 |
G11C16/08;H01L27/092;H01L21/8234;G11C16/24;H01L27/02;H01L27/115 |
主分类号 |
G11C16/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A semiconductor memory device comprising:
a memory cell; a peripheral circuit configured to drive the memory cell; and a protection element, wherein the peripheral circuit includes a first p-type MOS transistor including a gate electrode and a gate insulating film having a first film thickness, a second p-type MOS transistor including a gate electrode and a gate insulating film having a second film thickness, and an n-type MOS transistor, wherein the gate electrode of the first p-type MOS transistor is connected to the protection element, and wherein the gate electrodes included in the second p-type MOS transistor and the n-type MOS transistor are connected only to an impurity region of another transistor or only to a gate electrode of the another transistor. |
| 地址 |
Tokyo JP |
