| 发明名称 |
MEMORY AND METHOD OF OPERATING THE SAME |
| 摘要 |
A memory includes a plurality of memory blocks, a plurality of sensing circuits, a plurality of global bit lines, a common pre-charging circuit and a selection circuit. Each global bit line of the plurality of global bit lines is coupled to at least one of the memory blocks by a corresponding sensing circuit of the plurality of sensing circuits. The common pre-charging circuit is configured to individually pre-charge each global bit line of the plurality of global bit lines to a pre-charge voltage. The selection circuit is configured to selectively couple the common pre-charging circuit to a selected global bit line of the plurality of global bit lines. |
| 申请公布号 |
US2016019939(A1) |
申请公布日期 |
2016.01.21 |
| 申请号 |
US201514870402 |
申请日期 |
2015.09.30 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
YANG Jung-Ping;CHENG Hong-Chen;CHIU Chih-Chieh;HUANG Chia-En;LEE Cheng Hung |
| 分类号 |
G11C7/12;G11C7/10 |
主分类号 |
G11C7/12 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory, comprising:
a plurality of memory blocks; a plurality of sensing circuits; a plurality of global bit lines, each global bit line of the plurality of global bit lines being coupled to at least one of the memory blocks by a corresponding sensing circuit of the plurality of sensing circuits; a common pre-charging circuit configured to individually pre-charge each global bit line of the plurality of global bit lines to a pre-charge voltage; and a selection circuit configured to selectively couple the common pre-charging circuit to a selected global bit line of the plurality of global bit lines. |
| 地址 |
Hsinchu TW |
