SIDE WALL BIT LINE STRUCTURES

摘要

Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

主权项

1. A non-volatile memory, comprising:
a select gate pillar; an adjustable resistance local bit line pillar; a dielectric region arranged between the select gate pillar and the adjustable resistance local bit line pillar; a first word line; and a first portion of a memory element layer arranged between the adjustable resistance local bit line pillar and the first word line.