INSTRUCTION AND LOGIC FOR ADAPTIVE EVENT-BASED SAMPLING

摘要

A processor includes a core and an event-based sampler. The core includes logic to execute and retire an instruction. The event-based sampler includes logic determine a subset of a plurality of execution data of the processor from a register. The register includes bits specifying a subset of execution data. The event-based sampler further includes logic to selectively collect the determined subset of execution data upon retirement of the instruction and to store the selectively collected execution data.

主权项

1. A processor, comprising:
a core including a first logic to execute and retire an instruction; and an event-based sampler including:
a second logic to determine a subset of a plurality of execution data of the processor from a register, the register including bits specifying a subset of execution data;a third logic to, upon retirement of the instruction, selectively collect the determined subset of execution data; anda fourth logic to store the selectively collected execution data.