| 摘要 |
The invention concerns a method for monitoring transactions in an on-chip system comprising at least one main master module, at least one secondary master module, at least one slave module and a bus connected to each module, the bus comprising interconnection means to make at least one common slave module communicate with at least one main master module and with at least one secondary master module, the method comprising the following steps implemented during each transaction between a secondary master module and a common slave module: starting a counter upon initial detection of a transaction start signal, waiting for a final detection of a transaction end signal within a predefined time T, closing the transaction if the time tc that has elapsed since starting the counter is greater than predefined time Tmax, and reinitialising the counter. |
| 主权项 |
1. A transaction-monitoring method in a system on chip comprising at least one primary master module (Ma), at least one secondary master module (M1, . . . , Mi, . . . , Mk), at least one slave module (S1, . . . , Sj, . . . , Sn) and a bus (B) connected to each module by a communication link, the bus (B) comprising interconnection means for having a common slave module (Sj) communicate with at least one primary master module (Ma) and with at least one secondary master module (M1, . . . , Mi, . . . , Mk), lower priority than the primary master module to access the common slave module, the method comprising the following steps conducted during each transaction between a selectively secondary master module (Mi) and a common slave module (Sj):
startup (COUNT) of a counter during initial detection (DET1) of a transaction start signal (U1), wait (WAIT) for final detection (DET2) of a signal (U2) of transaction completion in a predetermined period Tmax, closure (TERM) of the transaction if the time elapsed tc from the startup of the counter is greater than the predetermined period Tmax, reset (RESET) of the counter. |
