AUTO-TRACKING UNSELECTED WORD LINE VOLTAGE GENERATOR

摘要

Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.

主权项

1. A method for operating a non-volatile memory, comprising:
generating a plurality of unselected word line voltages using a replica adjustable resistance bit line structure, the replica adjustable resistance bit line structure includes a replica adjustable resistance local bit line and a replica select gate, the replica adjustable resistance local bit line is connected to a replica global bit line, the replica global bit line is set to a selected bit line voltage during a memory operation; and performing the memory operation on a memory array, the memory array includes a first word line and a first global bit line, the first global bit line is connected to an adjustable resistance bit line structure that includes an adjustable resistance local bit line and a select gate, a first memory cell is arranged between the adjustable resistance local bit line and the first word line, the memory array includes a plurality of unselected word lines, a plurality of unselected memory cells is arranged between the adjustable resistance local bit line and the plurality of unselected word lines, the memory operation includes applying a selected word line voltage to the first word line and applying the selected bit line voltage to the first global bit line while the adjustable resistance local bit line is set into a conducting state, the memory operation includes applying the plurality of unselected word line voltages to the plurality of unselected word lines while the adjustable resistance local bit line is set into the conducting state.