| 摘要 |
The present disclosure pertains to a solid-state imaging element, a DA converter, a sample-and-hold circuit, and electronic equipment which enable reduction of a settling period in a sample-and-hold drive. In a sampling period, a sampling switch is maintained in an ON state to transfer a bias voltage to a hold capacitor, and in a hold period, the sampling switch is maintained in an OFF state to cause the hold capacitor to hold the bias voltage. In addition to the aforementioned drive, sampling is constantly performed for a predetermined fixed period immediately after an operation by which a current that flows in a current source for generating the bias voltage changes. This technology is applicable to, for example, CMOS image sensors. |
