发明名称 ELECTRONIC APPARATUS WITH SLEEP FUNCTION
摘要 PROBLEM TO BE SOLVED: To reduce power consumption in a sleep mode.SOLUTION: An electronic apparatus with sleep function comprises: a key panel 2 on which plural keys 21 are arranged; an FPGA 3 for scanning the key panel 2 for acquiring key scan information related to a depression state of the keys 21; and a CPU 4 which is operated independently from the FPGA 3, and is connected so as to perform sending-receiving with the FPGA 3. The FPGA 3 has a normal mode and a sleep mode, and when any one of the keys 21 is depressed during the normal mode, the FPGA 3 sends an interruption signal to the CPU 4 for sending the key scan information to the CPU 4, and when a specific key 21A is depressed, the FPGA 3 is transited to the sleep mode. During the sleep mode, only when the specific key 21A is depressed, the FPGA 3 sends the interruption signal and the key scan information to the CPU 4 and then is transited to the normal mode.
申请公布号 JP2016012198(A) 申请公布日期 2016.01.21
申请号 JP20140132782 申请日期 2014.06.27
申请人 JAPAN RADIO CO LTD 发明人 SUGISAKI YUGO;TAKEATSU YOSHIO
分类号 G06F3/02;G06F3/023;G06F3/0489;H03M11/20;H04M1/73 主分类号 G06F3/02
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