发明名称 半導体装置
摘要 A novel logic circuit which retains data even when power supply is stopped is provided. Further, a novel logic circuit with low power consumption is provided. In the logic circuit, a comparator comparing two output nodes, a charge retaining portion, and an output-node-potential determining portion are electrically connected to each other. Thus, the logic circuit can retain data even when power supply is stopped. In addition, the total number of transistors included in the logic circuit can be reduced. Further, a transistor including an oxide semiconductor and a transistor including silicon are stacked, whereby the area of the logic circuit can be reduced.
申请公布号 JP5844688(B2) 申请公布日期 2016.01.20
申请号 JP20120114385 申请日期 2012.05.18
申请人 株式会社半導体エネルギー研究所 发明人 八窪 裕人;長塚 修平
分类号 H03K19/096;H01L21/822;H01L27/04;H01L29/786;H03K3/356;H03K5/08;H03K19/0952;H03K19/20 主分类号 H03K19/096
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