Clock distribution architecture for logic tiles of an integrated circuit and method of operation thereof

摘要

An integrated circuit includes a plurality of logic tiles, wherein each logic tile includes a plurality of edges and is configurable to connect with adjacent logic tile. Each logic tile includes a plurality of input/output clock paths, wherein each input/output clock path is associated with a different edge of the logic tile. The plurality of input/output clock paths include a plurality of input clock path, each input clock path configurable to receive a tile input clock signal from an adjacent first logic tile, and a plurality of output clock paths, each output clock path configurable to output a tile output clock signal to an adjacent second logic tile. An output clock path includes a u-turn circuit to receive a tile clock signal having a first predetermined skew and provide a tile clock signal having a second predetermined skew.

主权项

1. An integrated circuit comprising:
a plurality of logic tiles, wherein each logic tile includes a plurality of edges and, during operation, is configurable to connect with at least one logic tile adjacent to each edge of the logic tile, and wherein each logic tile includes:
a plurality of input/output clock paths, wherein each input/output clock path is associated with a different edge of the logic tile, the plurality of input/output clock paths include:
a plurality of input clock paths, each input clock path configurable to receive a tile input clock signal from a connected adjacent first logic tile, anda plurality of output clock paths, each output clock path configurable to output a tile output clock signal to a connected adjacent second logic tile, wherein at least one of the output clock path includes:
a u-turn circuit, connected to or in an associated output clock path, to (i) receive a tile clock signal having a first predetermined skew relative to the tile output clock signal and (ii) provide a tile clock signal with a second predetermined skew;clock generation circuitry, coupled to the u-turn circuit of the output clock path, to receive the tile clock signal from the u-turn circuit and generate a tile clock based thereon; andprogrammable logic circuitry, coupled to the clock generation circuitry, to receive the tile clock and perform operations based thereon.