| 发明名称 | Sub-rate low-swing data receiver | ||
| 摘要 | A receiver is adapted to receive an input signal having a first voltage swing and to generate an output signal having a second voltage swing, the output signal being indicative of the input signal, the second voltage swing being greater than the first voltage swing. The receiver includes a first sub-rate receiver block and at least a second sub-rate receiver block. A receiver clock is divided into a first sub-rate clock phase and at least a second sub-rate clock phase, the first sub-rate clock phase being used to drive the first sub-rate receiver block and the second sub-rate clock phase being used to drive the second sub-rate receiver block. Each of the first sub-rate receiver block and the second sub-rate receiver block includes at least one gated-diode sense amplifier. | ||
| 申请公布号 | US9240789(B2) | 申请公布日期 | 2016.01.19 |
| 申请号 | US201213600534 | 申请日期 | 2012.08.31 |
| 申请人 | International Business Machines Corporation | 发明人 | Friedman Daniel J.;Liu Yong;Tierno Jose A. |
| 分类号 | H03K19/0175;H03K19/0185 | 主分类号 | H03K19/0175 |
| 代理机构 | Ryan, Mason & Lewis, LLP | 代理人 | Dougherty Anne V.;Ryan, Mason & Lewis, LLP |
| 主权项 | 1. A receiver adapted to receive an input signal having a first voltage swing and to generate an output signal having a second voltage swing, the output signal being indicative of the input signal, the second voltage swing being greater than the first voltage swing, the receiver comprising: a first sub-rate receiver block; and at least a second sub-rate receiver block, wherein a receiver clock is divided into a first sub-rate clock phase and at least a second sub-rate clock phase, the first sub-rate clock phase being used to drive the first sub-rate receiver block and the second sub-rate clock phase being used to drive the second sub-rate receiver block; and further wherein each of the first sub-rate receiver block and the second sub-rate receiver block comprises at least one gated-diode sense amplifier. | ||
| 地址 | Armonk NY US | ||