Capacitive sensor integrated onto semiconductor circuit

摘要

There is disclosed a capacitive sensor on a passivation layer of a semiconductor circuit such as an ASIC, and a method for manufacturing such sensor. The system and method may comprise: forming a bottom electrode layer and landing pad on a portion of the passivation layer located over active circuitry of the ASIC; forming a gas sensitive layer onto the bottom electrode layer and the landing pad; creating a via through the gas sensitive layer to expose a portion of the landing pad; forming a top electrode layer onto the gas sensitive layer, wherein the top electrode layer completely overlays a surface area of the bottom electrode layer, and wherein the forming process for the top electrode layer deposits a portion of the top electrode layer into the via hole, thereby forming an electrical connection between the top electrode layer and the landing pad.

主权项

1. A method for manufacturing a capacitive sensor on a passivation layer of a semiconductor circuit, the passivation layer having openings which expose a first bond pad and a second bond pad comprising:
forming a metal layer onto the passivation layer and patterning the metal layer to form a bottom electrode and landing pad and metal traces connecting the bottom electrode and the landing pad to their respective bond pads, the bottom electrode being positioned so that it is located over a portion of the semiconductor circuit with active circuitry; forming a gas sensitive layer onto the bottom electrode and the landing pad; creating a via through the gas sensitive layer to the landing pad; forming a porous top electrode onto the gas sensitive layer electrically connected to the landing pad through the via, wherein a portion of the top electrode completely overlays the surface area of the bottom electrode and an other portion of the top electrode is in contact with the landing pad.