发明名称 |
VC-2 decoding using parallel decoding paths |
摘要 |
Methods, devices and systems that perform VC-2 decoding are disclosed. In an embodiment, a VC-2 decoder includes three parallel data paths including top-band, current-band and bottom-band data paths. The top-band data path performs variable length decoding (VLD), inverse-quantization (IQ) and inverse-DC-prediction (IDCP) processing of a top compressed data-band. The current-band data path performs VLD, IQ and IDCP processing of a current compressed data-band. The bottom-band data path performs VLD, IQ and IDCP processing of a bottom compressed data-band. Additionally, the decoder includes a three-level inverse discrete wavelet transform (IDWT) module to perform IDWT processing to synthesize decoded source pixel values in dependence on partially-decompressed top, current and bottom data-bands produced using the three parallel data paths. The decoder also includes a slice-bytes equalizer, a bit-stream first-in-first-out (FIFO), a scan conversion FIFO, and a module that inserts horizontal and vertical blanking periods into data received from the scan conversion FIFO. |
申请公布号 |
US9241163(B2) |
申请公布日期 |
2016.01.19 |
申请号 |
US201313851821 |
申请日期 |
2013.03.27 |
申请人 |
INTERSIL AMERICAS LLC |
发明人 |
Zhou Caizhang;Chen Ting-Chung;Huang Chia-Chun |
分类号 |
H04N7/12;H04N11/02;H04N11/04;H04N19/126;H04N19/196;H04N19/157;H04N19/174;H04N19/42 |
主分类号 |
H04N7/12 |
代理机构 |
Vierra Magen Marcus LLP |
代理人 |
Vierra Magen Marcus LLP |
主权项 |
1. A decoder comprising:
three parallel data paths including a top-band data path, a current-band data path, and a bottom-band data path,
the top-band data path configured to perform variable length decoding (VLD), inverse-quantization (IQ) and inverse-DC-prediction (IDCP) processing of the top compressed data-band;the current-band data path configured to perform VLD, IQ and IDCP processing of the current compressed data-band; andthe bottom-band data path configured to perform VLD, IQ and IDCP processing of the bottom compressed data-band; and a three-level inverse discrete wavelet transform (IDWT) module configured to perform IDWT processing to synthesize decoded pixel values in dependence on partially-decompressed top, current and bottom data-bands produced using the three parallel data paths; wherein the three-level IDWT module includes a pipelined two-dimensional (2-D) IDWT synthesis filter that is implemented using N overlapped one-dimensional (1-D) IDWT filters, wherein N is a number of 1-D IDWT filters that are executed consecutively to generate a 2-D IDWT result. |
地址 |
Milpitas CA US |