Bipolar logic gates on MOS-based memory chips

摘要

A system for using selectable-delay bipolar logic circuitry within the address decoder of a MOS-based memory includes a MOS-based memory, which includes an array of a plurality of memory cells configured to store data; an address decoder including bipolar logic circuitry, where the address decoder is configured to accept a word including a plurality of bits and access the array of memory cells using the word; where the bipolar logic circuitry includes a plurality of bipolar transistor devices, where at least one bipolar transistor device has an adjustable gate bias and is configured to accept an input, wherein the gate bias is adjusted based on the input, where the gate bias determines a selectable gate delay.

主权项

1. A system, comprising:
a MOS-based memory, comprising:
an array of a plurality of memory cells configured to store data;a MOS-based address decoder configured to:
accept a word comprising a plurality of bits; andaccess the array of memory cells using the word;a bipolar-based address decoder comprising bipolar logic circuitry, wherein the bipolar-based address decoder is configured to:
accept a word comprising a plurality of bits; andaccess the array of memory cells using the word; andmemory controller circuitry configured to:
accept a selection input; anduse the selection input to select between the MOS-based address decoder and the bipolar-based address decoder.