发明名称 Enabling hardware acceleration in a computing device during a mosaic display mode of operation thereof
摘要 A method includes providing a memory unit in a computing device already including a number of processors communicatively coupled to a memory through a system bus, and providing a non-system bus based dedicated channel between the number of processors and the memory unit. The method also includes rendering a different video frame and/or a surface on each processor of the number of processors, and leveraging the memory unit to store a video frame and/or a surface rendered on a processor therein through the non-system bus based dedicated channel. Further, the method includes copying, to other processors, the stored video frame and/or the surface rendered on the processor from the memory unit through the non-system bus based dedicated channel, and scanning out, through the number of processors, the video frame and/or the surface rendered on the processor following the copying to enable display thereof on a corresponding number of displays.
申请公布号 US9239699(B2) 申请公布日期 2016.01.19
申请号 US201314102326 申请日期 2013.12.10
申请人 NVIDIA Corporation 发明人 Jotshi Praful;Agrawal Arpit
分类号 G09G5/00;G06F15/16;G06F3/14;G06T1/60;G06T1/20 主分类号 G09G5/00
代理机构 Zilka-Kotab, PC 代理人 Zilka-Kotab, PC
主权项 1. A method comprising: providing a memory unit in a computing device already comprising a plurality of processors communicatively coupled to a memory through a system bus, each processor of the plurality of processors having a corresponding memory location in the memory that is specific to the processor and each processor of the plurality of processors being connected to a corresponding one of a plurality of displays; providing a non-system bus based dedicated channel between the plurality of processors and the memory unit such that the plurality of processors share the memory unit; for each processor of the plurality of processors: rendering, by the processor, a different at least one of: a video frame and a surface,storing, through the system bus by the processor in the memory location of the memory corresponding to the processor, the rendered at least one of: the video frame and the surface,storing, through the non-system bus based dedicated channel by the processor in the shared memory unit, the rendered at least one of: the video frame and the surface, wherein each of the other processors of the plurality of processors copy the rendered at least one of: the video frame and the surface from the shared memory unit to the memory location of the memory corresponding to the other processor, such that each processor of the plurality of processors has a copy of the rendered at least one of: the video frame and the surface stored the corresponding memory location of the memory; for each processor of the plurality of processors, scanning out, from the corresponding memory location to the corresponding display, the rendered at least one of: the video frame and the surface, to enable display thereof on the plurality of displays in a mosaic display mode, where the plurality of processors is presented to an operating system executing on the computing device as a single logical processor.
地址 Santa Clara CA US