finFETs containing improved strain benefit and self aligned trench isolation structures

摘要

A first array of semiconductor fins and a second array of semiconductor fins are provided on a bulk semiconductor portion of a bulk semiconductor substrate. Each semiconductor fin of the first and second arrays is spaced apart by a first gap, and the outermost semiconductor fins of the first and second arrays of semiconductor fins are spaced apart by a second gap that is wider than the first gap. A sacrificial material is formed which completely fills the first gap, but not the second gap. An etch is employed to provide trenches into the bulk semiconductor portion which have sidewall surfaces self aligned to sidewall surfaces of sacrificial spacer structures that are formed during this etch. A trench isolation structure is formed into each trench and thereafter a functional gate structure is formed surrounding each semiconductor fin.

主权项

1. A method of forming a semiconductor structure comprising:
providing a first array of semiconductor fins on a first surface of a bulk semiconductor portion and a second array of semiconductor fins on a second surface of said bulk semiconductor portion, wherein each semiconductor fin of said first and second arrays is spaced apart by a first gap, and outermost semiconductor fins of said first and second arrays of semiconductor fins are spaced apart by a second gap that is wider than said first gap; depositing a sacrificial material completely filling each first gap with said sacrificial material, while not completely filling each second gap with said sacrificial material; forming a trench into a portion of said bulk semiconductor portion that is located under each second gap, wherein each trench has sidewall surfaces self aligned to sidewall surfaces of a sacrificial spacer structure that is formed in each second gap during said forming said trench; forming a trench isolation structure into each trench; and providing a functional gate structure surrounding a portion of each semiconductor fin of said first and second arrays of semiconductor fins.