AC stress methods to screen out bit line defects

摘要

A number of techniques for determining bit line related defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Defects related to bit line to NAND string contacts are determined by application of an AC stress mode along bit lines, followed by a defect detection operation. If the AC stress is applied to be out of phase on adjacent bit lines, this can also be used to accelerate bit line to bit line defects. The subsequent defect determination phase can include an erase operation followed a read to determine whether the NAND strings of the erased block read as erased, a process that can also be followed by a program and subsequent read to further check for defects.

主权项

1. A method of determining defects in a non-volatile flash memory circuit having a NAND type architecture, the memory circuit having an array of NAND strings each having a plurality of memory cells and formed into a plurality of erase blocks, each of the NAND strings connectable by an associated one of a plurality of bit lines to one of a plurality of sense amps, the method comprising:
performing a bit line stress operation, including applying a series of voltage pulses to a set of one or more bit lines by the sense amps connected thereto; and subsequently performing a defect determination operation, including
performing an erase operation on one or more blocks having a first set of NAND strings connected along the set of bit lines;subsequently performing a first read operation on the first set NAND strings of the erased blocks connected along the set of bit lines to determine whether the first set of NAND strings read as being erased; andin response to determining that one or more of the first set of NAND strings do not read as erased, determining the associated bit lines as being defective.