发明名称 Apparatus, method and system for asymmetric, full-duplex communication
摘要 Techniques and methods for performing asymmetric, full-duplex communication via a signal line. In an embodiment, a transceiver includes transmit circuitry to transmit a first signal via a node coupled to a signal line, where the first signal is transmitted concurrently with the transceiver receiving a second signal via the node at a substantially different data rate than that of the first signal. In another embodiment, signal processing circuitry of the transceiver detects a composite signal at the node, the composite signal including a combination of the first signal and the second signal. Based on the combination of the first signal and the second signal, the signal processing circuitry generates a processed signal, including the signal processing circuitry reducing a contribution by the first signal. The processed signal is provided to receiver circuitry of the transceiver.
申请公布号 US9240878(B2) 申请公布日期 2016.01.19
申请号 US201414165345 申请日期 2014.01.27
申请人 Lattice Semiconductor Corporation 发明人 Velitheri Rahul;Agrawal Vinayak;Sharma Namrta;Tirunagari Prashanth;Manchikalapudi Manjusha
分类号 H04L5/14;H04B1/56 主分类号 H04L5/14
代理机构 Fenwick & West LLP 代理人 Fenwick & West LLP
主权项 1. A first device comprising: a first transceiver configured to perform, with a second device coupled to the first device, asymmetric full-duplex communication of a first signal and a second signal, the first transceiver including: first transmitter circuitry configured to transmit the first signal from the first device via a first node while the second device transmits the second signal to the first node,wherein a superimposed signal of the first signal and the second signal is formed at the first node:signal processing circuitry coupled to the first node, the signal processing circuitry configured to generate a third signal from the superimposed signal, including the signal processing circuitry to reduce a contribution by the first signal; andfirst receiver circuitry coupled to receive the third signal from the signal processing circuitry, wherein one of the first signal and the second signal includes a stable portion comprised of two or more consecutive placeholder bits which each have the same logic level, wherein an exchange of the stable portion is concurrent with a transition time of the other of the first signal and the second signal.
地址 Portland OR US