Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode

摘要

Implementations herein involve control I/O buffer enable circuitry and/or features of saving power in standby mode. In illustrative embodiments, aspects of the present innovations may be directed to providing low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.

主权项

1. A semiconductor device comprising:
an array of memory cells; a control-peripheral circuit including an internal-peripheral circuit coupled to the array of memory cells; an i/o-peripheral circuit coupled to the array of memory cells; and a clock frequency detected control-i/o buffer enable circuit coupled to the i/o-peripheral circuit; wherein the clock frequency detected control-i/o buffer enable circuit includes a clock frequency detector and a control-i/o buffer enable circuit; and wherein a first reference signal provided to the clock frequency detector is associated with a band gap reference circuit.