发明名称 Providing bus resiliency in a hybrid memory system
摘要 In a hybrid memory system that includes a host memory controller and a non-volatile memory DIMM, where the DIMM is coupled to the host memory controller by a memory bus, the DIMM includes non-volatile memory, a DIMM bus adapter, and a local memory controller, the local memory controller is configured to control memory accesses within the DIMM, the DIMM bus adapter is configured to adapt the local memory controller to the bus for memory communications with the host memory controller in accordance with a bus protocol, bus resiliency may be provided by: discovering, by the DIMM bus adapter, a memory error in the DIMM; providing, by the DIMM bus adapter to the host memory controller, an indication of an error by emulating a hardware error native to the bus protocol; and performing, by the host memory controller, one or more resiliency measures responsive to the indication of the error.
申请公布号 US9239807(B2) 申请公布日期 2016.01.19
申请号 US201314066776 申请日期 2013.10.30
申请人 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. 发明人 Kochar Sumeet;Ono Makoto
分类号 G06F11/00;G06F13/16;G06F11/07;G06F11/26 主分类号 G06F11/00
代理机构 Kennedy Lenart Spraggins LLP 代理人 Lenart Edward J.;Brown Katherine S.;Kennedy Lenart Spraggins LLP
主权项 1. A method of providing bus resiliency in a hybrid memory system, the hybrid memory system comprising a host memory controller and a non-volatile memory DIMM (Dual Inline Memory Module), the DIMM coupled to the host memory controller by a memory bus, the DIMM comprising non-volatile memory, a DIMM bus adapter, and a local memory controller, the local memory controller configured to control memory accesses within the DIMM, the DIMM bus adapter configured to adapt the local memory controller to the bus for memory communications with the host memory controller in accordance with a bus protocol, the method comprising: discovering, by the DIMM bus adapter, a memory error in the DIMM; providing, by the DIMM bus adapter to the host memory controller, an indication of an error by emulating a hardware error native to the bus protocol; and performing, by the host memory controller, one or more resiliency measures responsive to the indication of the error.
地址 Singapore SG