发明名称 Group III-N nanowire transistors
摘要 A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.
申请公布号 US9240410(B2) 申请公布日期 2016.01.19
申请号 US201113976413 申请日期 2011.12.19
申请人 Intel Corporation 发明人 Then Han Wui;Chau Robert;Chu-Kung Benjamin;Dewey Gilbert;Kavalieros Jack;Metz Matthew;Mukherjee Niloy;Pillarisetty Ravi;Radosavljevic Marko
分类号 H01L27/088;H01L29/66;H01L29/775;H01L29/778;H01L29/786;H01L29/78;B82Y10/00;H01L29/06;H01L29/20 主分类号 H01L27/088
代理机构 Blakely, Sokoloff, Taylor & Zafman LLP 代理人 Blakely, Sokoloff, Taylor & Zafman LLP
主权项 1. A group III-N transistor, comprising: a nanowire disposed on a substrate, wherein a longitudinal length of the nanowire further comprises: a channel region of a first group III-N material;a source region electrically coupled with a first end of the channel region; anda drain region electrically coupled with a second end of the channel region, a gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the channel region, and a second group III-N material disposed between the first group III-N material and gate stack along at least a portion of the channel region.
地址 Santa Clara CA US