| 主权项 |
1. A processor comprising:
a plurality of execution cores, each having a local storage to store a last monitored address for an execution thread when the execution thread is to issue a monitor request; and a distributed cache having a plurality of distributed cache portions, each cache portion to store data corresponding to an address of a memory storage location, the cache portion also including state storage to store monitor requests and associated states: wherein responsive to receipt of a monitor request for the address, the cache portion is to record in the state storage a speculative state for a monitor state machine of the cache portion for the execution thread, and to transition the monitor state machine from an idle state to the speculative state; responsive to receipt of an mwait request for the address, to record in the state storage a wait-to-trigger state for the monitor state machine and to transition the monitor state machine from the speculative state to the wait-to-trigger state, and to send a monitor-wake event responsive to receipt of a write request for the address while the monitor state machine is in the wait-to-trigger state and to record in the state storage the idle state for the monitor state machine; and responsive to receipt of a monitor request for a second address while the monitor state machine is in the speculative state, to maintain the monitor state machine in the speculative state, and responsive to receipt of a write request for the second address while the monitor state machine is in the speculative state and the second address is stored in the cache portion to transition the monitor state machine to the idle state. |
