Asymmetric stressor DRAM

摘要

A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell.

主权项

1. A method of forming a semiconductor structure comprising:
forming a capacitor in a semiconductor substrate; forming an access transistor on said semiconductor substrate, wherein a source region of said access transistor is electrically shorted to an inner electrode of said capacitor, and a gate stack structure of said access transistor comprises a gate dielectric, a semiconductor material portion, and a gate dielectric cap; concurrently recessing a cavity in said drain region and a first portion of said gate dielectric cap that is proximal to a drain region, while a second portion of said gate dielectric cap that is distal from said drain region is not recessed; and forming a stressor structure within said cavity, said stressor structure generating asymmetric stress across a body region of said access field effect transistor.