Array and moat isolation structures and method of manufacture

摘要

An array or moat isolation structure for eDRAM with heterogeneous deep trench fill and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method further includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method further includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method further includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method further includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.

主权项

1. A structure, comprising:
a deep trench having sidewalls and a bottom in a DRAM array having a first critical dimension; a deep trench having sidewalls and a bottom in a moat region having a second critical dimension, larger than the first critical dimension; a dielectric node lining at least a portion of the sidewalls and an entire a bottom of the deep trench in the DRAM array and at least a portion of the sidewalls and an entire a bottom of the deep trench in the moat region; a metal filling the first critical dimension of the deep trench in the DRAM array, formed over the dielectric node; a metal lining over the dielectric node in the deep trench in the moat region, wherein the metal lining has a dimension smaller than that of the metal filling the first critical dimension of the deep trench in the DRAM array; and a Si material formed over the metal in the deep trench in the moat region, wherein the metal in the DRAM array is lower than the metal lining in the moat region due to RIE lag.