| 摘要 |
The present invention relates to a semiconductor memory apparatus. The semiconductor memory apparatus comprises: a raw address control unit which outputs an address as a raw address in response to a refresh signal and the address or outputs a counted signal as the raw address, and generates an auto precharge signal and a spare bank active signal in response to the refresh signal and a bank active signal; and a bank control unit which generates the bank active signal in response to an active signal, a precharge signal, the bank active signal, the auto precharge signal, and the spare bank active signal. |
