SYSTEM AND METHOD FOR AUTOMATIC DETECTION OF POWER UP FOR A DUAL-RAIL CIRCUIT

摘要

A dual-rail memory circuit having a sleep generation circuit configured to prevent undesired currents from being generated during power-up and while transitioning power states. When a dual-rail memory circuit is powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in a dual-rail memory circuit may be used to precisely control an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.

主权项

1. A memory, comprising:
first voltage node configured to ramp up toward a first voltage magnitude; a second voltage node having a second voltage magnitude that is greater than the first voltage magnitude; and a sleep mode generation circuit configured to hold a sleep signal at a first value until the first voltage node reaches the first voltage magnitude.