| 摘要 |
The present invention is provided with: a component element (1) obtained by alternately stacking semiconductor ceramic layers (3) formed from an SrTiO3-based grain boundary insulated semiconductor ceramic, and internal electrode layers (4a, 4b); and external electrodes (2a, 2b) which are electrically connected, at both ends of the component element (1), to the internal electrode layers (4a, 4b). The internal electrode layers (4a, 4b) are provided with lead-out sections (7, 8) which are lead out to one end surface (5) or another end surface (6) of the component element (1). The interval (a) between end surfaces (9, 10) of the internal electrode layers (4a, 4b) and the end surfaces (5, 6) of the component element (1), the interval (b) between side surfaces (13, 14) of the internal electrode layers (4a, 4b) and side surfaces (15, 16) of the component element (1), and the thickness (t) of each of the semiconductor ceramic layers (3) satisfy the relationships 2≤a/t≤10 and 2≤b/t≤5. Accordingly, a stacked semiconductor ceramic capacitor with varistor function is achieved which exhibits excellent reliability, is capable of inhibiting a reduction in insulation properties even if ESD repeatedly occurs, and is capable of ensuring desired electrical characteristics. |
