| 摘要 |
PROBLEM TO BE SOLVED: To provide a device configured to switch clock speed for multiple links running at different clock speeds and to provide a method of switching the clock signal.SOLUTION: A frequency divider 110 divides a plurality of clock signals 132a, 132b, 132c of different frequencies from a source clock signal. A clock switching controller 200 selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal 140 at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports. |
