NON-VOLATILE MEMORY WITH A SINGLE GATE-SOURCE COMMON TERMINAL AND OPERATION METHOD THEREOF

摘要

The present invention discloses a non-volatile memory with a single gate-source common terminal and an operation method thereof. The non-volatile memory comprises a transistor and a capacitor structure both embedded in a semiconductor substrate. The transistor includes a first dielectric layer, a first electric-conduction gate and several first ion-doped regions. The capacitor structure includes a second dielectric layer, a second electric-conduction gate and a second ion-doped region. The memory may further comprise a third ion-doped region below the second dielectric layer. The first and second electric-conduction gates are electrically connected to form a single floating gate of the memory cell. The source and second ion-doped region are electrically connected to form a single gate-source common terminal. The present invention greatly decreases the area and control lines of the memory cell and thus effectively reduces the cost thereof.

主权项

1. A non-volatile memory with a single gate-source common terminal, comprising
a semiconductor substrate; a transistor including a first dielectric layer, a first electric-conduction gate and a plurality of first ion-doped regions, wherein said first dielectric layer is disposed on said semiconductor substrate, and wherein said first electric-conduction gate is stacked on said first dielectric layer, and wherein said first ion-doped regions are respectively disposed at two sidessides of said first electric-conduction gate to function as a source and a drain; and a capacitor structure including a second dielectric layer, a second ion-doped region and a second electric-conduction gate, wherein said second dielectric layer is disposed on said semiconductor substrate, and wherein said second electric-conduction gate is stacked on said second dielectric layer, and wherein said second ion-doped region and said first ion-doped regions are doped with an identical type of ions, and wherein said second ion-doped region is only disposed at one side of said second dielectric layer, and wherein a channel is formed below said second dielectric layer, and wherein said first electric-conduction gate and said second electric-conduction gate are electrically connected to form a single floating gate, and wherein said source and said second ion-doped region are electrically connected to form a single gate-source common terminal.