SEMICONDUCTOR DEVICES INCLUDING INSULATING EXTENSION PATTERNS BETWEEN ADJACENT LANDING PADS AND METHODS OF FABRICATING THE SAME

摘要

A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls toward the substrate along the insulating spacers such that lower portions of the opposing sidewalls are free of the extension patterns. A plurality of buried contact patterns are provided on the substrate between the lower portions of the opposing sidewalls of adjacent pattern structures. Related fabrication methods are also discussed.

主权项

1. A semiconductor device comprising:
a plurality of pattern structures that are spaced apart from one another on a support layer and comprise at least one insulating spacer having an upper width smaller than a lower width; a plurality of insulating extension patterns on the at least one insulating spacer of the pattern structures, wherein an upper width of the extension patterns is greater than a lower width of the extension patterns; a plurality of contact patterns on the support layer between the pattern structures and the extension patterns; and a plurality of conductive patterns on upper and lateral surfaces of the pattern structures and electrically connected to the contact patterns.