STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND ASSOCIATED METHODS

摘要

A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

主权项

1. A semiconductor die assembly, comprising:
a package support substrate; a first semiconductor die having a peripheral region and a stacking region; a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die; a thermal transfer unit having a first portion attached to the peripheral region of the first die, a second portion attached to the first portion by an adhesive, and a cavity defined by the first and second portions, wherein the second die is within the cavity such that the second die is spaced apart from the first portion by a gap; and an underfill material in the cavity, wherein the underfill material has a fillet that fills at least a lower region of the gap between the first portion of the thermal transfer unit and the second die.