Described is a memory bit-cell comprising: a storage node; an access transistor coupled to the storage node; a capacitor having a first terminal coupled to the storage node; and one or more negative differential resistance devices coupled to the storage node such that the memory bit-cell is without one of a ground line or a supply line or both.
申请公布号
WO2016007135(A1)
申请公布日期
2016.01.14
申请号
WO2014US45695
申请日期
2014.07.08
申请人
INTEL CORPORATION;MORRIS, DANIEL H.;AVCI, UYGAR E.;RIOS, RAFAEL;YOUNG, IAN A.
发明人
MORRIS, DANIEL H.;AVCI, UYGAR E.;RIOS, RAFAEL;YOUNG, IAN A.