DISCRETE POWER CONTROL OF COMPONENTS WITHIN A COMPUTER SYSTEM

摘要

Systems and methods for discrete power control of components within a computer system are described herein. Some illustrative embodiments include a system that includes a subsystem with a plurality of components (configurable to operate at one or more power levels), a control register (coupled to the plurality of components) including a plurality of bits (each uniquely associated with a one of the plurality of components), and a power controller coupled to, and configurable to cause, the plurality of components to operate at the one or more power levels. The power controller asserts a signal transmitted to the subsystem, commanding the subsystem to transition to a first power level. A first of the plurality of components, associated with an asserted bit of the control register, operates at a second power level corresponding to a level of power consumption different from that of the first power level indicated by the power controller.

主权项

1. A processor system comprising:
(A) processor core circuitry having power control leads and memory control and status register control leads; (B) power control circuitry having processor leads coupled with the power control leads of the core circuitry and having a certain number of power control outputs; (C) first memory circuitry having the certain number of power control inputs; (D) memory control and status register circuitry having a first set of the certain number of register positions coupled to the memory control and status register leads of the core circuitry and having an output for each one of the first set of register positions; and (E) decode logic circuitry having inputs coupled to the power control outputs of the power control circuitry, having an input coupled to the output of each register position, and having decode outputs coupled to the power control inputs of the first memory circuitry, the decode logic coupling one power control output from the power control circuitry and an output for one register position to one decode output.