CACHED PHY REGISTER DATA ACCESS

摘要

Ethernet physical sublayer (PHY) devices each provide PHY register data. One or more of the Ethernet PHY devices are connected to each of one or more management data input/output (MDIO)/management data clock (MDC) interfaces to which a number of MDIO/MDC controllers are connected. Each MDIO/MDC controller polls a corresponding MDIO/MDC interface to receive the PHY register data from the one or more Ethernet PHY devices connected thereto. The MDIO/MDC controllers store portions of the PHY register data received from the Ethernet PHY devices to a memory to which an interface is connected. A processor connected to the interface accesses the portions of the PHY register data stored to the memory. The processor can retrieve the portions of the PHY register data over the interface more quickly than the MDIO/MDC controllers can retrieve the PHY register data over the MDIO/MDC interfaces.

主权项

1. A device comprising:
a plurality of Ethernet physical sublayer (PHY) devices, each Ethernet PHY device to provide PHY register data; one or more management data input/output (MDIO)/management data clock (MDC) interfaces, one or more Ethernet PHY devices of the Ethernet PHY devices connected to each MDIO/MDC interface; a plurality of MDIO/MDC controllers, each MDIO/MDC controller connected to and to poll a corresponding MDIO/MDC interface of the MDIO/MDC interfaces to receive the PHY register data from the one or more Ethernet PHY devices connected to the corresponding MDIO/MDC interface; a memory to which the MDIO/MDC controllers are to store portions of the PHY register data received from the Ethernet PHY devices; an interface connected to the memory; and a processor connected to the interface to access the portions of the PHY register data stored to the memory.