CORRELATED MULTIPLE SAMPLING CMOS IMAGE SENSOR

摘要

A CMOS image sensor including at least one pixel and one circuit arranged to receive, on a first node of the circuit, an analog signal representative of the luminosity level received by the pixel, the circuit being capable of successively acquiring 2n samples of said signal, n being an integer greater than or equal to 1, and of delivering, on a second node of the circuit, an analog signal having a value equal to the average of the values of said samples, without generating an intermediate signal having a value greater than the value of the largest acquired sample.

主权项

1. A CMOS image sensor comprising at least one pixel and one circuit arranged to receive, on a first node of the circuit, an analog signal representative of the luminosity level received by the pixel, the circuit being capable of successively acquiring 2n samples of said signal, n being an integer greater than or equal to 2, and of delivering, on a second node of the circuit, an analog signal having a value equal to the average of the values of said samples, without generating an intermediate signal having a value greater than the value of the largest acquired sample, the circuit comprising:
first and second capacitors, the second capacitor having a first electrode connected to the first node via a first switch, and a second electrode connected to a node of application of a reference potential, and the first capacitor having a first electrode connected to the second node and connected to the first electrode of the second capacitor via a second switch, and a second electrode connected to a node of application of the reference potential; n−1 branches, each comprising two switches in series between the first electrode of the second capacitor and the first electrode of the first capacitor, and a capacitor connecting the junction point of the two switches of the branch and a node of application of the reference potential; and a control unit capable of controlling the switches to successively acquire 2n samples of the voltage at the first node in the n+1 capacitors, and of delivering, across the second capacitor, a voltage equal to the average of the acquired samples.